An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism

tive to superscalar architectures [5][8][12][13]. Strengths of an on-chip MP architecture are threefold. First, an MP can exploit different level parallelism, thread-level parallelism (TLP), in addition to ILP. Second, the complexity can be suppressed using simple processors. This ensures a high clock rate. Third, communication latency can be significantly reduced using an on-chip network. These strengths have possibility that MPs outperform superscalar processors. On the other hand, the weakness is that a traditional MP is not efficient enough to exploit TLP in integer programs, the most important applications for computers. In general, coarse-grained TLP is little available due to complex and frequent control and data dependences in an integer program; only fine-grained TLP is available. Performance improvement by exploiting fine-grained TLP requires efficiency. One of critical problems in the efficiency is the reduction of overhead of communication and synchronization among processors. An on-chip network is obviously beneficial to this problem, but this is not enough because communication and synchronization through memory locations is still large overhead [5]. Register-based communication and synchronization mechanisms [2][5][12] are proposed to further reduce the overhead , ins tead o f t r ad i t iona l memory-based mechanisms. The register-based mechanisms directly communicate register values among processors, eliminating memory accesses. These mechanisms also support fast synchronization on the register file. Although register-based mechanisms significantly reduce the overhead, they still have a problem: those mechanisms interfere with exploiting ILP within a single thread at the expense of the overhead reduction of synchronization. Abstract